FAQ LSI

LSI products are registered in the public list of CISTEC (Center for Information on Security Trade Control) as the non-applicable products. Products on this public list can clear the customs by the publication number without submitting the non-applicability certification. Please contact NPM sales representative sales office for the publication number.

Yes, they fall under the Catch-All Control. Please make catch-All judgment at your company.

They are non-CCC standard products. The HS code is 8542.31.100.

Inside LSIs, many flip-flop (F/F) elements are used to memorize the signal state, so it is not certain whether the memory state of each elements will be '0' or '1' (indefinite state) when the power turns on. In such a state, the circuit cannot start its operation. By inputting the reset signal, all element states become the default states at the time of design, so the subsequent circuit operation can be certain.

Input it when the power is turned on. After the power is turned on, the status of all output terminals, such as the pulse output terminal, remains indefinite status until the reset signal is input. In addition, some LSI models are equipped with general-purpose I/O port pins. Due to the reset process, these general-purpose port terminals should become input ports (they may be output ports until the reset signal is input). If they are output ports, they may be short-circuited with other output circuits externally. Even if a short-circuit occurs, a LSI may not be damaged immediately. However, the LSI will gradually generate heat due to overcurrent, and will be damaged if it exceeds the storage temperature.

To prevent the noise from entering the Reset pin during operation, which causes malfunction, reset input has a built-in noise filter. The noise filter operates with the reference clock (CLK), therefore, a clock input is required while the reset signal is ON. The required number of clocks varies depending on the LSI model. Please check the user's manual. Also, there is a delay between turning on the power and start outputting the clock in a crystal oscillator for clock generation. So, the reset signal need to be turned off after securing more time than outputting the required number of clocks after the oscillation starts. When using a reset IC for monitoring the power-supply voltage, select the IC that will be reset-released after the delay time when the voltage rises to the rated voltage, so that the Reset should be released after the specified number of clock signals have been input.

No. Some LSI models have Reset Command, but if they have never input the reset signals, the circuit that interprets the command from the CPU may not operate properly. Be sure to input the reset signal when the power is turned on.

If the default state of F/F(flip-flop) is equal to the state at the reset input, the LSI may possibly operate. However, the default state of F/F may change due to fluctuation of ambient temperature or power supply voltage, and the LSI may become inoperable.

Some CPUs are capable of outputting clocks externally. However, clocks are not output until the initialization program starts after a CPU is released from reset state. Therefore, if the reset signal of a CPU is shared with the reset signal of a LSI, the clocks will not be input while the reset signal is input. So, when sharing a CPU's clock with a LSI , create a circuit so that the reset signal to a LSI can be controlled by the output port of a CPU, and reset the LSI after clocks are output from the CPU. Please note that a LSI may generate heat before a reset signal is input, so please reset it as soon as possible.

It can be any frequency as long as it is below the maximum frequency described in the manual. However, it may not be possible to set the speed magnification to an integer multiple.

You can stop it unless any glitch noises occur while stopping and restarting the motor. During stopping, the current consumption becomes almost zero, and the register setting value is retained. Please note that CPU-Interface circuitry also stops while the clock stops.

The accuracy of reference clock frequency is equal to the accuracy of the operation time such as speed accuracy or acceleration/decelerate​action​ time of output pulse trains. It is not related to the number of pulses (positioning accuracy). So, you can use a ceramic oscillator as long as you keep the accuracy you need. The specified number of reference clocks must be input while the reset input is in the ON state, which is the same as the crystal oscillator.

Our LSIs require the clock even during a reset, but the clock output may stop until a CPU executes the initialization software. If it is stopped, please input a reset signal to the LSI from the general-purpose output port of the CPU after the clock output starts.

You can connect it to the LSIs with clock input pins capable of 5 V input. However, the duty ratio can be different from the standard value of an oscillator due to the difference of threshold voltages, so make sure that the standard of clock width of the LSI is satisfied.

There is no problem if you meet the three conditions in "DC characteristics" of the electrical characteristics described in the user's manual: input capacity, low level input current, and high level input current.
Also, you need to consider the following points:
1. Make the clock lines as short as possible.
2. Do not wire the power line that generates noise parallel to the clock line.
3. Strengthen the GND line as much as possible.
4. Make the clock line thicker.

They are not specified, but 50 ns or less is recommended.

The reset signal must be input. Although the LSI may appear to be operating normally without the signal inputting, errors may occur due to individual differences in LSIs or changes in the ambient temperature.

In some LSI products that have general-purpose I/O ports, the I/O ports may be output ports before inputting the reset signal. This may result in a short-circuit with the external output circuit, causing the LSI and an external circuit to generate heat. Please turn on the reset signal as soon as possible (within 1 second) after the power is on. In addition, reference clock inputs are required for the reset process.

Check the absolute maximum ratings. There is no restriction when VDD is not related as the standard value or the condition. If the relation to VDD is described, follow the description. When creating 3.3 V from 5 V, "3-terminal regulator method" is preferable to "Switching power supply method" because the response is quicker.

The LSI can be connected if the connecting pin of the LSI is 5V-tolerant and the input voltage (VIH) of the CPU is satisfied by the output voltage (VOH) of the LSI. Although the LSI is pulled up to 5 V externally, the signal voltage does not exceed 3.3 V.

Do not fix CS to GND (CS=GND). There is a possibility of malfunction because the usage is not assumed at the time of LSI designing.

If you add a software-timer to the CPU program, you can control a wait request without connecting WRQ input. The timer-time varies depending on the LSI model. Please refer to the user's manual.

For safety, pull up only CS, RD, and WR pins with about 10 kΩ register to set the default level to High. LSI may generated heat during floating states.

Do not do that as it is dangerous. The default state is created after the reset pin goes low level and more than the specified number of reference clock signals are input. The port may be output before resetting, and the output level at that time cannot be defined. So, if general-purpose ports are connected to each other, the output pins may be short-circuited, resulting in heat generation and damages. There is a risk of damaging LSI if the crystal oscillator is damaged, even if the circuit configuration in question dese not usually cause a problem.

Please do the following process.
(1) Input pins: Connect to VDD or GND by pull-up or pull-down, or connect directly.
(2) Input/Output pins: Connect to VDD or GND by pull-up or pull-down.
(3) Output pins: Leave them OPEN for use.

You are correct. Attaching external pull-up resistors, LSIs are more resistant to noise. Attaching pull-up resistors can prevent floating.

Please check the standard values mentioned in the user's manual as it varies depending on the LSI product. For PCL6045BL, the maximum output pulse frequency is 1/3 of the reference clock frequency, and the maximum input frequency of 90-degree phase difference encoder is 1/4 of the reference clock frequency. However, the encoder has a phase error of approximately ±45 degrees, the maximum output pulse frequency is 1/6 of the reference clock frequency when an error is taken into consideration. Therefore, when high-speed is required, reduce the encoder resolution to count by multiplying by two or four.

An error is detected when EA and EB inputs change simultaneously (=within one cycle of the reference clock). (The phase difference of one cycle or more is required between EA and EB inputs.) However, this bit is to prevent count errors during operation, so it is unlikely to be an error even if A and B-phases change at the same time when the power is turned ON.

Yes, there are.
The output pulse train is generated by dividing the reference clock. If the division ratio is constant, the reference clock frequency is divided only to a specific frequency. Therefore, 1/N division and 1/ (N+1) division are mixed so that the average speed becomes the set speed. As a result, a cycle fluctuation occurs.

A quadratic function (y = ax^2) is used.

Yes, you can. For example, in PCL6045BL (CLK = 19.6608 MHz), RMG = 299 is 1 x, but RMG = 199 is 1.5 x.

There are cycle fluctuations in output pulse trains, and the lower the speed magnification, the smaller the fluctuation rate. We recommend to use as low a magnification as possible.

When a motor starts with acceleration, the acceleration starts immediately at the start inside a LSI. Therefore, even the first output pulse speed from the LSI will be faster than FL speed. In order to start at FL speed, the motor does not accelerate immediately at the start, but move several pulses at FL speed before start accelerating. The pulses to move several steps at FL speed is called "Idling pulse."

Our LSIs are not designed to change the speed magnification rate during operation. The output pulse cycle may be fluctuated or the output pulse may be temporarily interrupted.

When starting with acceleration, the motor "decelerates" from FL speed to FH speed. If you write a deceleration stop command when operating at FH speed, the motor will "accelerate" to FL speed and stop. In "preset operation", when reaching the slow-down point during operation at FH speed, the motor will "accelerate" to FL speed, resulting in a moving pattern that a trapezoid is turned upside down.

When the function is ON, you cannot calculate the travel time because the FH correction speed cannot be calculated accurately. Please set the FH correction function to OFF, and calculate the travel time by decreasing the FH setting speed using the calculation formula of manual FH correction.

In S-curve acceleration/deceleration with large moving amount, the maximum acceleration set by the acceleration/deceleration rate is reached at the time of intermediate speed between FL speed and FH speed. If the FH speed is lowered by the FH correction function, the intermediate speed section will be deleted, and a speed curve will be like connecting the acceleration (deceleration) start part and the acceleration (deceleration) end part. As a result, the higher the FH setting value is, the smaller the acceleration will be. So, the moving time will be longer.

If you write a start command with the moving amount "0", the operation is completed without outputting any pulses. It causes no particular problem.

They do not synchronize completely. The LSI speed is set for the pulser operation, and the pulse train of that speed is output in accordance with the pulser input. The faster the set speed, the less the time difference from the pulser input to the pulse output.

In the multiplier function of RENV6, the pulses corresponding to the multiplier setting are output at a time for each pulser input, and pulse output is paused until the next pulser input (burst-wave output). Therefore, cycle irregularity occurs. Please determine according to the operating conditions.

When you write the start command of the next operation, the operation starts with the data you write for the next operation. (PCL series). There is no error in the interpolation trajectory, but mechanical shock may occur in your machine since operation stops for a moment.

In 2-axis interpolation of pulse train control, the direction that can be moved in one step is only eight directions in 45-degree increments. In linear interpolation, a microscopically zigzag trajectory is created because motions in the long axis direction and motions in the 45-degree direction are mixed. The zigzag trajectory length can be longer than an ideal linear line. The synthetic speed constant control is a function to keep the speed constant in zigzag trajected, so the moving time to the point on the circumference varies depending on the angle. When the movement direction is 45-degree increment such as 0 degrees, 45 degrees, or 90 degrees, the moving time becomes constant because the interpolation trajectory does not become zigzag.

When synthetic speed constant control is OFF, the cycle of a long axis is constant, but the cycle of a short axis fluctuates by one period of a long axis pulse. When synthetic speed constant control is ON, the cycle of a long axis may also be √2 times.

When a motor is controlled by pulse trains, the motor can only stop at positions that are integral multiples of the travel amount (resolution) of one pulse. If you create a two-dimensional grids with the pitch of a resolution, you can only stop at the intersections. The actual movement trajectory moves on the intersections close to an arc. At that time, the difference between the movement trajectory and the ideal trajectory of a circular arc is "0.5 LSB" max. LSB is the unit of "Least Significant Bit " of a counter (RCUN1). The sign ± indicates that the trajectory moves on either side of the ideal trajectory. In other words, if the resolution is 0.5 mm/pulse, the difference between the movement trajectory and ideal trajectory will be ±0.25 mm.

It is the number to confirm the motion step which is being executed currently when you are setting the operation data of several steps ahead by using the pre-register. The number can be set by PRMD (operation mode) register, and the sequence number currently being executed can be checked by reading the main status. The sequence number has no effect on operation.

Undefined commands are processed in PCLs in the same way as 00h (NOP). However, since undefined commands have not been verified and may be used in future upgrades. Do not use undefined commands.

For the operation that stops automatically such as a positioning operation, the stop can be checked by SEND = 1. SRUN bit is used to check if the current operation is in progress or stopped. SEND bit becomes "1" when SRUN changes from operating to stopped. SSCM bit is used to check the write status of the start command. It is used to check when the operation does not start.

Yes, it can be used in RS-485. However, a GND line must be added to the communication line to connect the GND of all local devices, so the LSI may become vulnerable to noise.

A pulse transformer is use to isolate between the center and the local devices to eliminate the need for GND connections.

The specifications of both transformers are 1000 μH inductance and 6.0V•μS ET product. The pulse transformer that has the similar characteristics can be used, but confirm the operation by yourself before use. The maximum signal pulse width is 200 ns at 20 Mbps , 400 ns at 10 Mbps, 800 ns at 5 Mbps, and 1600 ns at 2.5 Mbps. The lower the speed, the greater the inductance and ET product are required. We have confirmed that both transformers can be used up to 2.5 Mbps.

The transmission distance varies depending on the characteristics of the line transceiver. We have not conducted an operation test over 100 meters. NPM can offer a hub product (MNET-HUB-A) which can be used for that length.

The type of cable (dielectric constant of insulator) has a great impact on communication quality. Do not use vinyl cables for wiring. A category 5 or higher LAN cable is recommended.

Pay attention to the following points.
・Communication speed is 20 Mbps or higher.
・Maximum number of connected nodes is greater than required.
・Protection circuit for output-short is built in.
・Output enable delay-time of a drive circuit is 50 ns or less. (at 20 Mbps)

It can be used, but in our experiments, the probability of communication error occurrence was high. We recommend to use a line transceiver IC of 5 V power supply.

0.25 W or more will be sufficient. We recommend 0.5 W or more.

If the frequency is 80 MHz or less, the LSI can operate at other frequencies. However, the all clock frequencies of local LSIs must be identical. Do not use a ceramic resonator and the like as the frequency needs accuracy.

No, there is no LSI that can handle input and output of analog signals directly. Connect A/D and D/A converters to G9002A or G9004A.

If you write the start command for the next operation (0050h to 0053h) after stopping, the operation starts with the previous operation data, not with the next operation data. Also, if you cannot write the next operation data in time during an interpolation operation, an error will occur in the interpolation trajectory. Use an interrupt (RSTS.ISBE) to monitor it. (G9103A and B)

If the same data is returned from the local devices at the same timing against the communication from the center device, it may operate normally, or an error may occur.

The new data is overwritten on the previous data.

Based on our experiments and experience, we specified to determine the broken wires and failures by three communication errors.

We do not recommend the connection. It only repeats the process of "Reset to Watchdog timer operation".

Not only in "own device", but it also occurs when occurring communication errors in other devices.